Physical Resource Matching Under Power Asymmetry

Manufacturing related variations are predicted to have a significant impact on power consumption for near future technology generations. Due to both die-to-die and within-die parameter variations, the power consumption of identically designed hardware resources can vary randomly on a per instance basis. This introduces fabrication induced asymmetry, which can undermine basic assumptions about power/performance balances in a design. Specifically, architects expect that superscalar pipeline resources and cores in a homogenous CMP design are truly homogenous when fabricated on a chip. In this paper, we describe implications that fabrication power asymmetry have on a CMP design with respect to the allocation and utilization of hardware resources and the mapping between applications and physical cores. We introduce hardware/software management techniques that can overcome power asymmetry by considering the dissimilar power profiles of physical resources under parameter variation.